The present invention relates to peak detectors and, more particularly, to a circuit and method for detecting the most positive peak level of a signal.
Peak detectors are usually used to track the most positive peak voltage level of a signal. Thus, the desired output of a peak detector typically represents the most positive peak voltage level of its input signal. However, most, if not all, prior art peak detectors are designed to detect the most negative peak voltage level of an input signal thereby constituting a need for inverters to implement a peak detector that detects positive peak voltage levels whereby the use of inverters creates additional offset errors.
The basic theory of a peak detector is to compare the input voltage level to the output voltage level to determine if the input signal has reached a new peak voltage level. If indeed the input signal has reached a new peak, the peak detector will respond in a manner to increase the voltage level of the output signal until it has attained the same voltage of the peak input signal. A common technique use by most peak detectors is a charge up a capacitor wherein the voltage across the capacitor represents the peak voltage level of the input signal so that when the input voltage falls below the output voltage, the capacitor maintains the peak input voltage level at the output of the peak detector.
Peak detectors can be evaluated with respect to attack time and power dissipation. Attack time is defined as the finite time required by a peak detector to adjust its output voltage level in accordance to a new peak voltage level occurring in the input signal. Attack time is dependent upon two main factors: the ability to prevent the switching transistors from entering saturation wherein the switching transistors compare the input voltage level to the output voltage level, and the speed at which the capacitor in the peak detector is charged up. Most, if not all, peak detectors have been unable to prevent the switching transistors from entering the saturation region thereby increasing the time required for the peak detector to respond to a new peak voltage level since a finite time is required to allow a saturated transistor to become active.
The speed at which the capacitor in the peak detector can be charged up is particularly important for rapidly changing input signals. A capacitor must charge up to the full peak voltage of the input signal level by the time the peak input level disappears or the true peak level will not have been recognized. Furthermore, the charge up time of a capacitor is related to the current through the capacitor by the following equation: EQU t.sub.cu =(V.sub.p .times.C)/I (1)
where
t.sub.cu is the charge up time of the capacitor C; PA1 V.sub.p is the peak voltage that we wish to obtain at the output; and PA1 I is the current through the capacitor C.
Therefore, a quick charge up time (t.sub.cu) requires a large current (I) thereby increasing the power dissipation of the peak detector. Most, if not all, peak detectors have satiated their required charge up time by simply increasing the power dissipation; however, if power dissipation is critical, compensation must result in an increased attack time.
Hence, what is needed is a peak detector that detects the positive peak voltage level of an input signal and having a quick attack time while minimizing power dissipation.